\vspace{10pt}
\section{Testing Cost Modeling For 3D ICs}\label{model}

In this section, we first present a basic cost model that captures the economics of testing in 3D IC design. We then discuss the impact of new issues raised by 3D stacking, including the use of different stacking strategies, new defect types during stacking, as well as the interaction between testing costs and fabrication costs of 3D ICs.

\subsection{Basic Cost Model of 3D Testing}
Our testing cost model is adapted from the 2D DFT model in~\cite{Nag2002}. For the sake of brevity, we mainly address the uniqueness due to 3D integration.
The testing cost of 3D ICs consists of four main components-preparation
cost, execution cost, test-related silicon
cost, and imperfect-test-quality cost. Hence, we
compute testing cost $C_{test}$ (per good chip) as~\cite{Nag2002}:
\begin{equation}
  C_{test} = C_{prep} + C_{exec} + C_{silicon} + C_{quality}
\end{equation}

$C_{prep}$ captures fixed costs of test generation,
tester program creation, and any design effort
for incorporating test-related features (all nonrecurring
costs, including software systems). Note that in 3D ICs, this may include
the preparation cost for pre-bond testing of TSVs.

$C_{exec}$ consists of costs of test-related hardware
such as probe cards and cost incurred by tester
use. Tester-use cost depends on factors including tester setup time, test execution time (as a function of die area
and yield), and capital cost of the tester (as a function of die
area and number of I/O pins) and capital
equipment depreciation rate. This should also be compensated if pre-bond TSV testing is applied.

$C_{silicon}$ is the cost required to incorporate DFT
features. We model this cost as a function of
wafer size, die size, yield, and the extra area
required by DFT.

$C_{quality}$ is the penalty due to the faulty chips that escape the test. This component exhibits increasing importance for 3D integration with the relatively low yield and high cost of 3D ICs.

\vspace{10pt}
\textbf{Test preparation cost for 3D ICs.}
For the cost of test preparation for 3D ICs, we start from the model presented in~\cite{Nag2002} for 2D cases and augment it for 3D IC integration. Generally, the preparation cost contains the test-pattern generation cost ($C_{test\_gen}$), tester-program preparation cost ($C_{test\_prog}$), and the additional design cost for ($C_{DFT\_design}$).

In 3D IC designs, different bonding technologies might be used to assemble die or wafer layers together into a single chip. For example, if W2W bonding is used, no pre-bonding test will be performed. In this case, all of the test-related preparations, including the DFT design, test-pattern generation and tester-program preparation, should target at the whole chip, instead of a single die. Therefore, the testing cost only applies to the final test after wafer bonding and sorting. The preparation cost for a W2W-bonded 3D chip can be calculated as:
\begin{equation}
\small
  C_{prep,W2W} = \frac{1}{Y_{W2W}}({{C_{DFT\_design}}+{C_{test\_gen} + C_{test\_prog}}}),
\end{equation}\\
where $Y_{W2W}$ denotes the final yield of the chip after bonding and will be discussed in the next sub-section.
% can be calculated as:
%$ Y_{final}=Y_{bond}^{N-1}\times{\prod_{i=1}^{N}{Y_i}}$.

If D2W bonding is used, each layer should be tested before bonding, so the preparation cost will be changed to:
\begin{eqnarray}
  C_{prep,D2W} = \frac{1}{Y_{D2W}}(Y_{N}C_{prep,N}+\sum_{i=1}^{N-1}{C_{prep,i}}).
\end{eqnarray}
where
\begin{equation}
C_{prep,i}=\frac{1}{Y_i}({C_{DFT\_design,i} + C_{test\_gen,i} + C_{test\_prog,i}}).
\end{equation}
where $N$ is the number of layers in the chip, $Y_i$ is the yield for each die before bonding, and $C_{DFT\_design,i}$, $C_{test\_gen,i}$, $C_{test\_prog,i}$ are calculated with regard to the area of each die using the 2D model in~\cite{Nag2002}. Note that layer $N$ is the bottom layer in the stack that is closest to IO pads, and it is usually tested only after bonding.

\vspace{10pt}
\textbf{Test execution cost for 3D ICs.}
The test execution cost is the total cost per chip of hardware consumption and the testing devices expense. In 2D IC testing, all individual ICs on a wafer should be tested before they are packaged. The wafer testing is performed by using a hardware called wafer prober or probe card. Therefore, the hardware cost for testing is mainly determined by the cost of probe cards~\cite{Nag2002}. We use $N_{probe}$ to represent the number of wafers a probe card can test and use $C_{probe}$ to denote the price of a probe card. Thus the hardware cost is calculated as:
\begin{equation}
C_{hw}=C_{probe}\lceil{V/N_{probe}}\rceil /V.
\end{equation}

 In plain terms, a chip with $n$ layer should be tested $n$ times for D2W stacking while only 1 time for W2W stacking. Thus, the hardware cost for 3D ICs can be summarized as
\begin{equation}
\left\{
\begin{array}{ll}
C_{W2W,hw}=C_{probe}\lceil{V_{chip}/N_{probe}}\rceil /V_{chip},\\
C_{D2W,hw}=C_{probe}\lceil{NV_{chip}/N_{probe}}\rceil /V_{chip}.
\end{array} \right.
\end{equation}

Besides the cost of probe cards, the cost of testing devices should also be considered in the execution cost. The cost of the testing device can be calculated as:
\begin{equation}
C_{device}=R_{test}T_{test}+R_{idle}T_{idle}.
\end{equation}
where $R_{test}$ is the cost rate of the testing devices when they are operating, containing the cost of operator, electricity, device depreciation, etc. $R_{idle}$ denotes the cost rate of the testing device when they are inactive, which is much smaller than $R_{test}$. $T_{test}$ and $T_{idel}$ are the testing time and the idle time of the testing device.

We denote the relationship between the testing rate and idle rate as: $R_{test}=\eta R_{idle}$, where $\eta$ is the proportion between the testing cost and idle cost and satisfies: $\eta\gg1$. Also, the testing time and idle time satisfy : $T_{test}+T_{idle}=T_{year}$, where $T_{year}$ is the total second number of one year. Also, the testing rate and idle rate are in proportion to the testing device's price. A testing device's unit price is :

\begin{equation}
Q=K_{capital}\cdot K_{pin}\cdot{\sqrt{{A_{die}}}}.
\end{equation}
where $K_{capital}$ is the average device price per pin and $K_{pin}$ is the average density of pins in a die.

Therefore, the cost rate of the testing devices for a 3D chip can be summarized as
\begin{equation}\label{eq:rexec}
R_{D2W,test,i}=\beta_{depr}K_{capital}\cdot K_{pin}\cdot{\sqrt{{A_i+A_{DFT,i}}}}~,\\
\end{equation}

\begin{equation}
\small
R_{W2W,test,i}= \left\{
\begin{array}{ll}
\beta_{depr}K_{capital}K_{pin}{\sqrt{{A_i}}} & if~i<N\\
\beta_{depr}K_{capital}K_{pin}{\sqrt{{A_{N}+A_{DFT}}}} & if~i=N
\end{array} \right.
\end{equation}
where $\beta_{depr}$ is the annual depreciation rate of the testing device.

The testing time can be simply modeled as:
\begin{equation}
T_{test}=T_{setup}+K_{ave\_t} A_{die}^2.
\end{equation}
where $K_{ave\_time}$ is a constant multiplier that relates testing time to the die area. Thus, the testing time for a 3D chip is:

\begin{equation}
T_{D2W,test,i}=T_{setup}+K_{ave\_t} (A_i+A_{DFT,i})^2.
\end{equation}

\begin{equation}
\small
T_{W2W,test,i}= \left\{
\begin{array}{ll}
T_{setup}+K_{ave\_t}{A_i}^2. & if~i<N\\
T_{setup}+K_{ave\_t}(A_{N}+A_{DFT})^2. & if~i=N
\end{array} \right.
\end{equation}

\vspace{10pt}
\textbf{Testing circuit overhead.}
%To make 3D IC designs commercially viable, the most critical step is in the
%final integration---which must ensure that only
%KGDs will be bonded and packaged. As the number
%of 3D layers increases, a random bonding strategy will
%never be economically practical, because it could decrease
%the overall yield exponentially. To effectively
%address this issue, designers must ensure that each individual
%die layer is designed to be testable before
%bonding takes place.
Testing circuits usually occupy a certain fraction of the total silicon area. In 3D integration with KGD testing (D2W or W2W stacking), since test structures have to be implemented in each layer, the total area overhead of the testing circuits will be larger than that of the 2D case, and the relative area overhead of the testing circuits increases as the number of total layers goes up. For a given die with DFT structures, we denote the area ratio between DFT circuits and the whole die by $\alpha_{DFT}$. For W2W stacking, we have $A_{DFT,total}= \alpha_{DFT} \cdot A_{2D}$, while for D2W stacking:

\begin{equation}\label{eq:dft1}
A_{DFT, i} = \alpha_{DFT} \cdot A_i = \alpha_{DFT}\cdot \frac{A_{2D}}{N}
\end{equation}
\begin{eqnarray}\label{eq:dft2}
A_{DFT, total} &=& \alpha_{DFT} \cdot A_{2D} + \sum_{i=1}^{N-1} A_{DFT, i} \nonumber\\
               &=& \alpha_{DFT} \cdot A_{2D}\cdot\frac{2N-1}{N}
\end{eqnarray}
Therefore, the DFT circuit overhead $A_{DFT, total}$ for D2W stacking is an increasing function of layer count $N$. The silicon cost for the DFT circuit overhead is given by:
%Therefore, the overhead factor $\alpha_{ovhd}$ is a function of layer count $n$.
%
%\begin{equation}
%  A_{overall} = \big(1 + \alpha_{ovhd}(n)\big)A_{2D} = A_{2D} + A_{DFT}(n)
%\end{equation}

\begin{equation}\label{eq:dft3}
  C_{silicon,D2W} = \frac{Q_{wafer}}{\pi R^2_{wafer}\beta_{waf\_die}}\bigg[\frac{A_{DFT,total}}{Y_{overall}}\bigg]
\end{equation}

\textbf{Imperfect test quality.}
For simplicity in modeling, we only model escape cost due to imperfect test quality.
The test escape rate is a function of fault coverage and the fault occurrence rate (or simply the yield) at a particular stage of test. Williams and Brown~\cite{Williams1981} give the escape rate, the ratio of the defective ICs that pass testing to all the ICs that pass testing, as

\begin{equation}\label{eq:fc}
  E_r = 1 - Y^{1-fc}
\end{equation}
where $f$ is fault coverage. The same relation stands for W2W stacking of 3D ICs. Similarly, if D2W stacking is used, the error rate will be changed to:
\begin{equation}
  E_{r,D2W} = 1 - \prod_{i=1}^{N}Y_i^{1-fc_i}
\end{equation}
where $Y_i$ and $fc_i$ are the yield and fault coverage for die in layer $i$, respectively.

The cost of imperfect test quality is then calculated by:
\begin{equation}
  C_{quality} = C_{penalty}\cdot E_r
\end{equation}
where $C_{penalty}$ is the economic penalty for allowing a defective IC to escape testing. Depending on the importance attached to escaping ICs, the penalty might be
as much as 10 times of the manufacturing cost of a good IC.


\subsection{The Impact of 3D Stacking Strategies on Chip Yield}
3D stacking strategies have significant impacts on the overall chip yield, which in turns affects the average cost per chip.
The yield model for a single die has been well investigated~\cite{Murphy1964,Michalka1990}.
%[A discussion of yield modeling with defect clistering circuit repair and circuits...]
Assuming that the defects are randomly distributed on a wafer, the probability of the number of defect dies in a wafer can be described as a binomial random variable and can be approximated by a Poisson random variable. Therefore, the yield of a die can be simply modeled as:
\begin{equation}\label{eq:yield}
  Y_P = e^{-D_0A_{die}}.
\end{equation}
where $D_0$ is the average density of the defect and $A_{die}$ is area of the certain chip.

However, it has been shown that the defects are usually not randomly distributed across the chip, but are always gathering in some certain areas. In this case, the die yield should be higher than the result of Equation (\ref{eq:yield}). Therefore, a compound Poisson distribution is proposed by Murphy~\cite{Murphy1964}, which applies a weighting function to modulate the original Poisson distribution.
% http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00056568&tag=1
A widely used weighting function is the Gamma function~\cite{Mercier2006}. The Gamma function based yield model is:
\begin{equation}
\label{eq:gamma}
  Y_G = \left( 1 + \frac{D_0A_{die}}{\alpha} \right)^{-\alpha}.
\end{equation}
The parameter $\alpha$ is defined as $\alpha=(\mu_D/\sigma_D)^2$ and depends upon the complexity of the manufacturing process. $D_0$ is the silicon defect density parameter. Obviously, the yield decreases exponentially with the increase of die area. Thus, the smaller dies in 3D IC design may result in higher yield than that of a larger 2D die and therefore reduce the cost.


To calculate the overall yield of a 3D chip, the following aspects should be taken into consideration:
\begin{itemize}
  \item For 3D ICs, both the die yield and the stacking yield should be consider at the same time. The defects exist in each die will certainly affect the overall chip yield of after stacking. At the mean time, an unsuccessful stacking operation can also cause a chip to fail.
  \item In 3D ICs, dies at different layer are not necessary to have the same size. As shown in Equation~(\ref{eq:gamma}), different die sizes will result in different yields.
  \item Stacking yield should be defined carefully. There are two sources of the stacking failure: (1) Failure results from imperfect TSVs; (2) Failure results from imperfect stacking operation. However, since the TSV-related failures have already been captured when calculating the stacking yield, they should not be counted as defects of a single die.
  \item Different stacking methods, such D2W stacking and W2W stacking, require different yield models.
\end{itemize}

\textbf{Yield model for W2W stacking.}
During W2W stacking, each die cannot be tested until the stacking is finished. The DFT circuitry is located at the bottom layer of the chip, which is closer to the IOs. Based on these considerations, the yield for W2W stacking can be modeled as:
\begin{eqnarray}\label{eq:Yoverall1}
  Y_{overall,W2W} = [1+\frac{D_0}{\alpha}(A_{N}+A_{DFT})]^{-\alpha}\cdot \nonumber\\
  \prod_{i=1}^{N-1}{Y_{S,W2W,i}}(1+\frac{D_0A_i}{\alpha})^{-\alpha}
\end{eqnarray}
where ${Y_{S,W2W,i}}$ denotes the stacking yield between layer $i$ and layer $i-1$, and $A_{DFT}$ is the area of DFT circuitry on the bottom layer.

\textbf{Yield model for D2W stacking.}
For D2W stacking design, a higher yield can be achieved by introducing KGD test. The dies in layer 1 to layer $N-1$ are tested separately before the stacking operation. Thus, during the stacking step, all these dies can be considered as ``good dies''. Thus the chip yield will be:

\begin{eqnarray}\label{eq:Yoverall2}
  Y_{overall,D2W} = [1+\frac{D_0}{\alpha}(A_{N}+A_{DFT,N})]^{-\alpha}\cdot \nonumber\\
  \prod_{i=1}^{N-1}{Y_{S,D2W,i}}
\end{eqnarray}
where $Y_{S,D2W,i}$ is the D2W stacking yield factor, which will be discussed in the next subsection.



%To evaluate the cost sensitivity of one chip to certain die yield, we calculate:
%\begin{eqnarray}
%\frac{d_{C_{W2W,chip}}}{d_{Y_k}}=-({Y_k}\prod_{i=1}^{N}Y_i{\cdot}{\prod_{i=1}^{N-1}Y_s})^{-1}\sum_{i=1}^{N}\frac{C_{wafer,i}}{N_{die,min}}.
%\end{eqnarray}
%
%
%\begin{equation}
%\small\small
%\frac{d_{C_{D2W,chip}}}{d_{Y_k}}= \left\{
%\begin{array}{ll}
%-{Y_{N}}\frac{C_{wafer,k}}{N_{die,k}}(Y_k)^{-2}\prod_{i=1}^{N}Y_{S,W2W,i}~~~~if~i<N \\
%\beta_{ave\_depr}K_{capital}K_{pin}^{\sqrt{{A_{N}+A_{DFT}}}}~~~~if~i=N
%\end{array} \right.
%\end{equation}
%
%-({\prod_{i=1}^{N-1}Y_s^2}{\cdot}{\prod_{i=1,i\neq k}^{N-1}Y_i^2})^{-1}\sum_{i=1}^{N}\frac{C_{wafer,i}}{N_{die,min}}.

\subsection{New Defect Types Due to 3D Stacking}

Because 3D integration incurs additional processing steps, such as TSV forming and bonding, new defect mechanisms (unique to 3D integration) must be addressed as part of a test strategy. First, in TSV-based 3D ICs, TSVs under manufacturing suffer from conductor open defects and dielectric short defects, thus the TSV failure rate is unwillingly high~\cite{Marinissen2009,Chen2009}.
Moreover, the thinning, alignment, and stacking of the wafers add extra steps to the manufacturing process. During bonding, any foreign particle caught between the wafers can lead to peeling, as well as delamination, which dramatically reduces bonding quality and yield. In addition, to maintain good conductivity and minimize resistance, the interconnect TSVs and micropads between wafers must be precisely aligned.
%Edge effects must also be considered in 3D IC testing because the edges between bonded wafers are more susceptible to chipping,
%peeling, and delamination, a problem unique to 3D IC manufacturing. Cracking can occur during the stacking process, especially because of loading forces, back-side grinding, and die thinning. Finally, random open defects can result from dislocations, oxygen trapped on the surface, voids formation, and mechanical failures.

Due to the new defect types brought in by 3D stacking, the stacking yield factor in Equations (\ref{eq:Yoverall1})-(\ref{eq:Yoverall2}) can be
modeled as:
\begin{eqnarray}\label{eq:Ybonding}
  Y_S & = & Y_{bonding}\cdot Y_{TSV} \nonumber\\
  &=&Y_{bonding}\cdot (1-f_{TSV})^{N_{TSV}}
\end{eqnarray}
where $Y_{bonding}$ captures the yield loss of the chip due to faults in the bonding processes, $f_{TSV}$ is the TSV failure rate, $N_{TSV}$ is the total number of TSVs, and $Y_{TSV}$ describes the rate of loss due to failed TSVs.

In current TSV process technology, $f_{TSV}$ varies from $50~ppm$ to $5\%$. A simple calculation shows that, given a design with 200 TSVs and a typical TSV failure rate of 0.1\%, the yield loss due to failed TSV will be as much as 20\%, which is barely acceptable. For this reason, designers have proposed several techniques, including pre-bond TSV testing~\cite{Chen2009} and redundant TSV insertion~\cite{Kwai2009} to mitigate the impact of high TSV failure rate.

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.45\textwidth]{./figures/prebond.pdf}\\
  \caption{Schematic of a pre-bond TSV testing circuit.}\label{fig:prebond}
%  \vspace{-10pt}
\end{figure}

\textbf{Pre-bond TSV testing.}
The current interconnection test proposed for 3D IC is done with two or more dies in a stack, which is good only for TSVs after bonding~\cite{Chen2009}. Since the yield of TSVs has a dramatic influence on overall chip yield, some pre-bond TSV testing schemes are needed in order to reduce the risk of bonding dies that have irreparable TSV failures. As via-first TSVs have one end that is not only floating but also buried in the wafer substrate before thinning and bonding, double-end probing for TSV resistance measurement becomes incapable. Alternatively, a single-end probing based TSV test method was proposed~\cite{Chen2009} to diagnose pre-bond TSVs with the parasitic capacitance measurements.

A detailed schematic of the TSV testing circuit is shown in Figure~\ref{fig:prebond}. The TSV is modeled as a conductor with its parasitic capacitance in a given range. If there is any defect in the TSV or in the insulator surrounding TSV, the measured parasitic capacitance will deviate from the nominal value. In this way, the faulty TSVs can be detected and the failure rate $f_{TSV}$ is greatly reduced. Correspondingly, the area overhead of the testing circuit will be translated to testing cost, as it increases $A_{DFT}$ in Equations (\ref{eq:dft1})-(\ref{eq:dft3}). The trade-off between $f_{TSV}$ and the increase of $A_{DFT}$ will then be explored in our 3D testing cost model.

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.45\textwidth]{./figures/tsv.pdf}\\
  \caption{Two TSV redundancy mechanisms~\cite{Kwai2009}.}\label{fig:tsv}
  \vspace{-10pt}
\end{figure}


\textbf{Redundant TSV insertion.} Another effective way to reduce the impact of faulty TSVs is to create TSV redundancy.
As shown in Figure~\ref{fig:tsv}-(a), a straightforward doubling redundancy of TSVs can tolerant any single TSV failure. However, it fails if both of the TSVs fail. In Figure~\ref{fig:tsv}-(b), the redundancy is enhanced by sharing the connectivity between adjunct TSVs with a set of multiplexes.

In a simple TSV redundancy scheme (without any multiplexors), the degree of redundancy $m$ is defined as how many TSVs are used for a single signal. The TSV yield and the TSV area with redundancy is then given by:
\begin{eqnarray}\label{eq:ftsv}
  Y_{TSV} = \big(1-(f_{TSV})^m\big)^{N_{TSV}},\\
   A_{TSV, redundant} = m\cdot A_{TSV}
\end{eqnarray}

For the redundant TSVs with multiplexors, a check-and-repair mechanism is required to configure the multiplexors for desired connections after TSV diagnosis. This will inevitably increase the testing cost. Since we have little knowledge about the complexity and cost of the multiplexer tuning, we do not include this overhead in our cost model. We use the simple redundancy scheme for analysis without loss of generality.

\begin{figure}
\centering
  % Requires \usepackage{graphicx}
  \includegraphics[width=0.35\textwidth]{./figures/dependency.pdf}\\
  \caption{Dependency graph of the key quantities in 3D IC cost model.}\label{fig:dependency}
  \vspace{-10pt}
\end{figure}

\subsection{Interaction with Fabrication Cost}

%Note, in the traditional 2D IC design, the yield can directly reflect the cost efficiency of a chip. For example, assuming the cost for a wafer is $C_{wafer}$, the yield of the die is $Y_{die}$, and the number of dies in a wafer is $N_{die}$, the cost for a chip (or a die) after testing can be calculated as:
%\begin{eqnarray}\label{eq:wafer}
%C_{chip}=\frac{C_{wafer}}{N_{die}Y_{die}}
%\end{eqnarray}
%
%However, 3D ICs always stack many dies into one chip. The estimation of a chip cost is far more complex than that of 2D ICs. For wafer-to-wafer stacking, the cost for a chip can be calculated as:
%\begin{eqnarray}
%C_{W2W,chip}=\sum_{i=1}^{N}\frac{C_{wafer,i}}{N_{die,min}Y_{overall,W2W}}.
%\end{eqnarray}
%which is similar to Equation~(\ref{eq:wafer}). This is because the wafer-to-wafer stacking do not implement testing before stacking. Nevertheless, the die-to-die staking model is much more complex:
%\begin{eqnarray}
%C_{D2W,chip}=\sum_{i=1}^{N}\frac{C_{wafer,i}}{N_{die,i}Y_{die,i}Y_{overall,D2W}}.
%\end{eqnarray}

The fabrication cost for 3D ICs has been analyzed in~\cite{Dong2009}. However, DFT-related cost concerns have not been touched yet. According to the discussions in previous sub-sections, incorporating DFT in 3D IC design will have significant impact on chip fabrication and total cost of chips.
Figure~\ref{fig:dependency} shows the dependencies between the key quantities in 3D IC cost model considering testing cost. We can see that testing cost is closely related to fabrication cost through the inclusion of TSVs and DFT structures. Both of the fabrication and testing costs have strong correlations with chip area and yield, and the trade-offs between all the quantities in the graph are to be explored by our 3D cost model.

To facilitate the total cost analysis, we first update the total chip area to be:
\begin{equation}\label{eq:aoverall}
  A_{overall} = A_{2D} + A_{DFT} + A_{TSV}*N_{TSV}
\end{equation}
where $A_{TSV}$ is the chip area occupied by a single TSV. $N_{TSV}$ is the TSV count, which can be estimated from $A_2D$ using a methodology similar to the one presented in~\cite{Dong2009}. With this we calculate $A_i$s in Equations (\ref{eq:rexec})-(\ref{eq:dft3}).

The total cost of 3D ICs is then calculated by:
\begin{equation}
  C_{total} = C_{fabrication} + C_{test}
\end{equation}
We reuse the fabrication cost analysis in~\cite{Dong2009} for estimation of $C_{fabrication}$ and calculate $C_{test}$ using the model presented in this paper. 